interrupt delay

[ABSF]

Refering to Fig 14-14 of section 14.5 Interrupts of the 16F628 datasheet. The interrupts from T0IF, INTF and RBIF has higher priority as they are only maskable by GIE. TMR1IF, TMR2IF, CCP1IF, CMIF, TXIF, RCIF and EEIF have lower priority and they're maskable by GIE or PEIE.

So during Timer1 interrupt in progress, is it to possible to be interrupted by CCP1 or timer2 interrupt in C language?

Allen

[ober]

Refering to Fig 14-14 of section 14.5 Interrupts of the 16F628 datasheet. The interrupts from T0IF, INTF and RBIF has higher priority as they are only maskable by GIE. TMR1IF, TMR2IF, CCP1IF, CMIF, TXIF, RCIF and EEIF have lower priority and they're maskable by GIE or PEIE.

Actually there is no priority base interrupt in PC16F, as what I know, at least for the time being, Microchip might change the architecture

Masking with extra PEIE is just to group up the interrupt. They are being divided into core interrupt (which is controlled by GIE and its IE only) and Peripheral interrupt which have extra bit PEIE to enable them.

So in other words, let's say timer 0 and timer 1 interrupt are being enabled. And at a time, T0IF (Timer 0) and TMR1IF (Timer 1) is flag because of interrupt condition happen, and this happen at the same time. Which interrupt is being served? Let's have discussion here I like discussion.

So during Timer1 interrupt in progress, is it to possible to be interrupted by CCP1 or timer2 interrupt in C language?

Very good question you have there allen, you are going deep now the answer is no, and again, let's start discussion.

[aurora]

Yup, agree with ober. 16F family can only run 1 interrupt routine at a time. So, if you have 1 interrupt in progress, other interrupts won't work. Not even C can help you.

But with 18F family, you can! It has this high/low priority interrupts. Low priority interrupt will be halt and jump to high priority interrupt once flagged. All you need to do is to assign CCP1 or timer2 as high priority interrupt, and timer1 as low priority interrupt.

From what I understand (from the datasheet), this is what happen during interrupt:
1. GIE will be clear as soon as an interrupt is flagged
2. Check individual interrupt register to identify which interrupt is enable
3. Run the interrupt routine
4. clear the interrupt flag
5. GIE is set

If two timer 0 and timer 1 happened to be flagged at the same clock, which one it will execute will depends which comes first in step 2.

[ABSF]

That's what I suspected too as I saw this sample program from my PIC book:

CODE: SELECT_ALL_CODE

ISR_ADDR         ;INTERRUPT ROUTINE ENTRY POINT
   BTFSS   INTCON, GIE         ;LOOP TILL GIE IS SET
   GOTO   ISR_ADDR
   PUSH         ;KEEP THE CONTENTS OF IMPORTANT REGISTERS
   BTFSC   INTCON, RFIB   ;CHANGE OF RB 4,5,6,7
   GOTO   ISR_PORTB
   BTFSC   INTCON, INTF   ;EXTERNAL INTERRUPT OCCURED?
   GOTO   ISR_RB0
   BTFSC   INTCON, TOIF   ;OVERFLOW OF TIMER TMR0?
   GOTO   ISR_TMR0
   BANK1         ;BANK1 BECAUSE OF EECON1
   BTFSC   EECON1, EEIF   ;WAITING TO EEPROM COMPLETED?
   GOTO   ISR_EEPROM
   BANK0
   ..................
ISR_PORTB
   :         ;SECTION OF CODE PROCESSING AN INTERRUPT
   :
   GOTO   END_ISR      ;JUMP TO EXIT OF AN ISR
ISR_RB0
   :         ;SECTION OF CODE PROCESSING AN INTERRUPT
   :
   GOTO   END_ISR
ISR_TMR0
   :         ;SECTION OF CODE PROCESSING AN INTERRUPT
   :
   GOTO   END_ISR
ISR_EEPROM
   :         ;SECTION OF CODE PROCESSING AN INTERRUPT
   :
   GOTO   END_ISR
END_ISR
   POP         ;BRING BACK THE CONTENTS OF IMPORTANT REGISTERS
   RETFIE         ;RETURN AND SETTING OF GIE BIT

On entry of the ISR routine, the program did not clear GIE, but start testing it to see if it is set so as to do the indivisual interrupt tasks based on interrupt source. So I guessed that the GIE had to be cleared upon an interrupt by hardware. And upon the exit of the ISR routine, the GIE was again set by hardware without program intervention. From this I guessed ONLY one interrupt is possible where any further one would be put on WAIT while the first one is executing.

this is what happen during interrupt:
1. GIE will be clear as soon as an interrupt is flagged
2. Check individual interrupt register to identify which interrupt is enable
3. Run the interrupt routine
4. clear the interrupt flag
5. GIE is set

Is #2 and #4 done by PIC hardware or software in 18F PIC?

So in other words, let's say timer 0 and timer 1 interrupt are being enabled. And at a time, T0IF (Timer 0) and TMR1IF (Timer 1) is flag because of interrupt condition happen, and this happen at the same time. Which interrupt is being served? Let's have discussion here I like discussion.

I agree with aurora on this one. As my attached program shows that whoever comes first would be served first and the next one would be kept waiting at the ertrance by the loop.

Hmmmm, that's a great lesson I learnt today. I will checked the 18F family datasheets soon and ask some more if I dont understand.

Thanks for clearing my doubts on this issue for the PIC 16F family.

Allen

[ABSF]

All you need to do is to assign CCP1 or timer2 as high priority interrupt, and timer1 as low priority interrupt.

You mean interrupt priority in 18F can be software assigned and not by hardware?
How did you do it?
May be I should be reading the datasheet first, then asking this question but I am just too curious to know.


Allen

[aurora]

#2 and #4 need to be done by software (from what i understand from the datasheet). But if you are writing in C, the compiler will take care of it. Only in assembly we have to write it.

The priority interrupt in 18F is one of its key feature, everything through hardware. Pretty cool eh?