PIC24FJ128GA306 sleep mode current: 16+ mA current consumpti

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PIC24FJ128GA306 sleep mode current: 16+ mA current consumpti

Postby mkioiu » Thu Sep 01, 2016 5:11 pm

Hello, Everyone,
I’m working on a migration from a design that used a 24FJ256GB110 to a similar design which uses a 24FJ128GA306. This design includes a sleep mode state where I need minimum power consumption for longer battery life. Both parts use the same firmware design with some conditional compiles for things like configuration bits and IO.

What I’ve noticed is that when I run the design on the 24FJ256GB110 I see a few hundred microamps on the VDD supply for IO and pic while the pic is in sleep mode. If I run on the 24FJ128GA306 I see 16+ mA.

If I hold the 24FJ128GA306 in reset, current on the VDD supply drops from 16+ mA to a few hundred microamps, which I believe suggests that the current consumption is coming from either the processor or IO driven by the processor when the pins and IO registers are not in reset states.

I can see the same behavior on multiple devices, so it’s not limited to a single chip or board issue.

I’m using the primary oscillator in my design when in the mode that is sleeping, switched from the Fast RC oscillator which is configured out of reset. My config bits are:
_CONFIG1(GWRP_OFF & JTAGEN_OFF & ICS_PGx3 & FWDTEN_WDT_SW & WINDIS_OFF & FWPSA_PR128 & WDTPS_PS4);
_CONFIG2(IESO_ON & FNOSC_FRC & OSCIOFCN_ON & POSCMD_HS & FCKSM_CSECMD & IOL1WAY_OFF);
_CONFIG3(SOSCSEL_OFF);
I’m entering sleep using the Sleep() macro defined in each part header file, which in both cases is the following define:
#define Sleep() {__asm__ volatile ("pwrsav #0");}

I remain in sleep for 16ms based on the watchdog timer settings. I can see that the oscillator stops during sleep mode every 16ms on either platform. If I toggle a pin before and after the Sleep() function I can see a 16 ms delay, so I believe the processor is stopped in the Sleep() function for at least this long. The duration of wakeup time between the two platforms is identical. Increasing the amount of time in sleep via the watchdog to the point where the processor sleeps indefinitely does not reduce current below 16 mA.

My suspicion after reading other forum posts about high current in sleep mode was that improperly configured IO was responsible for the additional current. However, I’ve checked and double checked my IO settings to confirm I don’t have something like a analog value on a digital input, or a digital output driving the wrong logic level, or a misconfigured IO pin. I haven't come up with any way to explain additional current draw by incorrect IO settings. I did find a few problems with analog voltages on digital inputs but after fixing this and verifying the registers were now set correctly I didn't see any difference in current consumption.

I’ve paused execution with the debugger and looked at differences in SFRs between the two different micros to see if there might be a peripheral that’s somehow being turned on and left on in sleep mode which might explain the difference in current. I don’t see differences between the two platforms related to peripherals being on or off.

Finally, I noticed the comments in several forum posts about ap note CE342 as a deep sleep example, and have built and run this on the 24FJ128GA310 (with some small adaptations for config bits). I see the same 16+ mA with this code.

I’m running out of ideas about things to try, hoping someone here will have some suggestions.
The pdf: http://www.kynix.com/uploadfiles/pdf879 ... 199424.pdf
Any suggestions will be much appreciated.
Best regards,
mkioiu
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