PIC18 configuration

[shahrul]

Can someone explain this configuration? What is different CPUDIV and PLLDIV?
If I use crystal 10MHz, how I want to increase to be 40MHz because PIC18F4550 can support up to 48MHz.
This configuration using Hi-Tech

CODE: SELECT_ALL_CODE

__CONFIG(1,USBOSC & CPUDIV1 & PLLDIV1 & HS  & FCMDIS & IESODIS);


[Idris]

This config using C18

CODE: SELECT_ALL_CODE

#pragma config FOSC = HSPLL_HS   // PLL, 10MHZ x 4 = 40MHz
#pragma config FCMEN = OFF
#pragma config IESO = OFF
#pragma config PWRT = OFF
#pragma config BOR = OFF
#pragma config WDT = OFF
#pragma config MCLRE = ON
#pragma config PBADEN = OFF
#pragma config DEBUG = OFF
#pragma config XINST = OFF
#pragma config LVP = OFF

Maybe you can change HS to HSPLL and ignore other '...DIV' bits

[shahrul]

But, answer here is different http://www.edaboard.com/thread246480.html
PLL is comes from 96MHz, then divide by 2 to make 48MHz.

[Idris]

PIC18F4550 is unique because it is USB compatible. The clock can be divide and multiple. I also program it before using Hi Tech C Compiler (Fire Fighting Robot 2011) and get headache. Finally just use C18 Compiler. hehe.

[robosang]

looking at the Oscillator diagram in the datasheet might help you. If you need to use the USB, you need to makesure the clock from PLLDIV (MUX) is 4MHz and the 96MHz PLL block with boost it to 96MHz and you can use further.

If you are using 10MHz, I doubt you can configure it for USB purpose. Anyway it seem you don want to use USB, you want the to use 40MHz for CPU only, right? You will not get 96MHz to divide by 2 for 48MHz. Why don use 12MHz and configure PLLDIV to be 3; or use 16MHz and PLLDIV to be 4, or use the common 20MHz and PLLDIV to be 5.